This invention relates generally to processor based systems, and more particularly, to methods and systems for providing low latency and scalable interrupt collection capabilities for processor based systems.
Exception and notification based interrupt schemes for utilization within processor based architectures have been in existence since the first microprocessor systems were put into use. The term processor, as used herein, refers to microprocessors, microcontrollers, ASICS, FPGAs, RISC-based processors, programmable logic, and any other processing device that may incorporate one or more interrupt signals and associating servicing (interrupt handling) routines. Minimizing the hardware latency of interrupt signals and minimizing the software interrupt handler response time necessary to identify each interrupt source has been the topic of many technical papers and patents.
As digital microprocessor based systems increase in complexity and size, improved interrupt collection architectures are needed that provide scalability, low latency, and minimal I/O pin count. As a practical example, real time systems that are used for command and control in space based applications need predictable interrupt latency, and the ability to support a large number of interrupt sources.